1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with a plurality of memory cells storing data.
2. Description of the Background Art
In a Magnetic Random-Access Memory (MRAM), memory cells include TMR (Tunneling Magneto Resistive) elements having a TNR effect. The MRAM includes a plurality of memory cells that are aligned and arranged at crossing portions of bit lines and digit lines, respectively. The TMR element includes magnetic thin films and a tunneling oxide film held therebetween, and has a resistance which takes a minimum value when directions of the magnetic moments of the upper and lower magnetic thin films are parallel to each other, and takes a maximum value when these direction are antiparallel.
The memory cell stores logical information in accordance with “0” and “1” that correspond to the parallel relationship of the magnetic moments of the upper and lower magnetic thin films and the antiparallel relationship thereof, respectively. Drive currents of the digit line and the bit line are configured to generate a magnetic field enough to switch the directions of the magnetic moments of the magnetic thin films, whereby the logical information can be written into the memory cell. The memory cell can permanently hold the logical information until the magnetic field exceeding a certain threshold changes the directions of the magnetic moments of the upper and lower magnetic thin films. Reading of the data from the memory cell is performed by detecting the directions of the magnetic moments of the upper and lower magnetic thin films, i.e., a magnitude of the resistance value of the TMR element.
When the drive currents of write current lines, i.e., the digit and bit lines exceed a certain threshold, the data can be written into the memory cell. However, when the drive current of the bit or digit line is excessively large, the magnetic field to be exerted on a write target memory cell may affect memory cells other than the write target memory cell, i.e., the memory cells such as memory cells in a half-selected state that are located on one of the bit and digit lines corresponding to the write target memory cell, and thereby may cause them to malfunction.
Among the memory cells, there are variations in threshold of the write current required for writing data into the memory cell, i.e., in thresholds of drive currents of the digit and bit lines. Therefore, such a method has been known (e.g., see U.S. Pat. No. 6,850,430 (patent reference 1)) that tunes the write current for correctly writing the data into each memory cell, i.e., for allowing writing of the data into each memory cell while preventing a malfunction of the memory cells other than the write target memory cell. Although the write current generally has a temperature dependence, no consideration is given to the temperature dependence of the write current in the method of tuning the write current disclosed in the patent reference 1.
For example, Japanese Patent Laying-Open No. 2004-185752 (patent reference 2) has disclosed a semiconductor memory device including a write circuit that supplies a write current having a temperature dependence for dealing with the temperature dependence of the write current.
Japanese Patent Laying-Open No. 2003-257175 (patent reference 3) has disclosed the following semiconductor memory device. A write current supply is supplied with a voltage produced by a temperature-compensated voltage supply circuit, and thereby provides a write current having a desired temperature dependence.
Japanese Patent Laying-Open No. 2004-288311 (patent reference 4) has disclosed the following semiconductor memory device. The semiconductor memory device includes a plurality of word lines formed in a first direction, a plurality of bit lines formed in a second direction perpendicular to the first direction, memory cells arranged at respective crossings of the word and bit lines and including magneto-resistance elements, a row decoder selecting the word line and a column decoder selecting the bit line as well as a write circuit that supplies first and second write currents to the word and bit lines selected by the row and column decoders, respectively, and writes the data into the selected memory cell arranged at the crossing of the selected word and bit lines. The write circuit changes current values of the first and second write currents according to the temperature.
Japanese Patent Laying-Open No. 07-211869 (patent reference 5) has disclosed the following semiconductor integrated circuit. For a DRAM internally provided with a down converter, a regular transistor gate voltage control circuit performs digital control on pMOS transistors arranged in parallel. However, the semiconductor integrated circuit disclosed in the patent reference 5 is not configured to deal with a temperature dependence of the write current.
Among the memory cells, variations generally occur in write current threshold at a certain temperature, and further, variations occur in temperature dependence of the write current threshold. More specifically, when the temperature changes, the write current threshold of each memory cell varies to a degree different from the other memory cells, and the relationship in magnitude of the write current threshold between the memory cells may be inverted. However, each of the semiconductor memory devices disclosed in the patent references 2-4 may enter such a situation that data cannot be written correctly into the memory cell at a temperature different from the temperature at which the write current was tuned, due to variations in temperature dependence of the write current threshold among the memory cells. Thus, the structures disclosed in the patent references 2-4 suffer from a problem that the structure cannot deal with the variations in temperature dependence of the write current threshold among the memory cells.